Z80 SBC Phase 1


So, I have shifted gears a little on the design. I am still using a large ROM that will be divided into selectable banks. Also, a 512K RAM is being used, but there is still no bank select circuitry as that can get a bit tricky. I have, however, finished a design for the board and ordered the prototype from JLCPCB. I won't share the design yet as I have not yet received them, so I do not know for sure that it works.

What has changed is that I am now using a motherboard/daughterboard configuration similar to some other retro designs on the net. The CPU, RAM, ROM, and clock circuitry are located on a motherboard that has four expansion slots on it. The expansion slots make all address, data, and control lines of the CPU available as well as eight I/O lines that are decoded on the main board. This provides each I/O device with 32 bytes of address space, but that could be further divided by additional circuitry on a daughterboard.

At this time, I have designed one daughterboard. It is a serial port for the computer to allow it to interface with the modern world. At this point, I have written a monitor program for the computer that can display and enter memory addresses. The monitor program takes far less than 8K, so for now, there will also be 56K of RAM available on the machine for programs. Bank switching has not yet been implemented and would require a redesign of the motherboard as RAM is located there.

I designed the boards themselves somewhat quickly to get moving forward. Fortunately, if I redesign the motherboard, the daughterboards will likely continue to be useful if I do not change the interface. Another option would be the ability to add a second type of interface that differs but also keep the original interface to allow the old boards to continue to work. In the future, I may move the CPU, RAM, and ROM to separate boards while keeping the glue logic on the mainboard. This, however, would require a separate interface or the use of some of the extra signals available on the current interface as there is not ROM/RAM select lines on the current interface.

I am currently waiting to receive some right angle pin headers to finish the serial board so that I can test everything.