Z80 SBC Phase 1

 

So, I have shifted gears a little on the design. I am still using a large ROM that will be divided into selectable banks. Also, a 512K RAM is being used, but there is still no bank select circuitry as that can get a bit tricky. I have, however, finished a design for the board and ordered the prototype from JLCPCB. I won't share the design yet as I have not yet received them, so I do not know for sure that it works.

What has changed is that I am now using a motherboard/daughterboard configuration similar to some other retro designs on the net. The CPU, RAM, ROM, and clock circuitry are located on a motherboard that has four expansion slots on it. The expansion slots make all address, data, and control lines of the CPU available as well as eight I/O lines that are decoded on the main board. This provides each I/O device with 32 bytes of address space, but that could be further divided by additional circuitry on a daughterboard.

At this time, I have designed one daughterboard. It is a serial port for the computer to allow it to interface with the modern world. At this point, I have written a monitor program for the computer that can display and enter memory addresses. The monitor program takes far less than 8K, so for now, there will also be 56K of RAM available on the machine for programs. Bank switching has not yet been implemented and would require a redesign of the motherboard as RAM is located there.

I designed the boards themselves somewhat quickly to get moving forward. Fortunately, if I redesign the motherboard, the daughterboards will likely continue to be useful if I do not change the interface. Another option would be the ability to add a second type of interface that differs but also keep the original interface to allow the old boards to continue to work. In the future, I may move the CPU, RAM, and ROM to separate boards while keeping the glue logic on the mainboard. This, however, would require a separate interface or the use of some of the extra signals available on the current interface as there is not ROM/RAM select lines on the current interface.

I am currently waiting to receive some right angle pin headers to finish the serial board so that I can test everything.

 

 

So, once I got the boards built and connected, I powered them on. I eagerly watched my terminal program... And nothing. I was not receiving any data at all.

Over several months, I would occasionally pull the boards out and try to check various signals, replace certain ICs, and in general, do a lot of trying to follow my schematics to find the problem. Then, I finally decided that I was going to purchase a 32 channel logic analyzer from Amazon. I received it and discovered that at 2 MHz, it could only capture those 32 channels for a fraction of a second. It had compression capabilities, but only with 16 channels. This was not ideal for me as I wanted to watch the address lines, data lines, and several signals. It was, however, what I had.

So, I started by checking the clock. (Yes, I had previously checked this with an oscilloscope.) The clock looked fine. I then connected up MREQ, and it seemed to be working. I then added my decoded chip enable lines for the ROM and RAM. That was not working correctly. (Or at least it seemed at the time.) Ultimately, I added the data lines, IOREQ, and the decoded IO line for the serial board.

First, I noticed that the data lines were always outputting FF, which is RST 38H on the Z80. This meant that the Z80 was constantly ReSTarting to $0038 and ended up reading from the same memory. I scratched my head at that for a bit, reprogrammed the flash ROM and tried again. I knew the Flash was programmed correctly, but it still had the same behavior. I then realized that my bank switches were set incorrectly (a stupid oversight). I flipped them to bank 0, and the bus started to work. I was able to see the correct data being read from the ROM, I could see the proper RD and WR signals being generated at the correct times. Appropriate data was being stored when it was supposed to be. (I couldn't tell if it was the right location as I did not have enough analyzer lines for address as well.)

With compression, I was able to read enough data that I could follow the execution of the program up through where the UART was being set up. IORQ was working, WR was asserted, but it was not selecting the correct device. (Well, technically it was when reading/writing to Port 0 on the UART.)

All this time, I had a working system, except for selecting the correct device. I pulled up the schematics and looked at the 74HCT138 that decodes the IO. I had put A0, A1, and A2 in to decode. It was supposed to have been A7, A6, and A5 which would provide 32 registers to 8 different IO devices. (This could be further divided on built daughterboards if necessary.) So, I cut some traces and ran some bodge wires. I plugged it back in to the PC (I had removed all of the test leads to solder, so this was an easier way to test since I believed I had found the problem), and I turned it on.

My screen displayed my welcome message and prompt. After working out some bugs in the software, I now have my very basic monitor program running on the DZ80! In fact, I have also built Tiny BASIC for it, and it works as well.